Wednesday Keynote Speaker

Norbert Wehn
Professor and Chair for Microelectronic System Design
University of Kaiserslautern, Germany

“The Memory Wall: Challenges and Solutions”

Norbert Wehn holds the chair for Microelectronic System Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern. He has more than 300 publications in various fields of microelectronic system design and holds 20 patents. Two start-ups spinout of his research group. His special research interests are VLSI-architectures for mobile communication, forward error correction techniques, low-power techniques, advanced SoC and memory architectures, 3D integration, reliability issues in SoC, IoT and hardware accelerators for big data applications.

Abstract: Current and emerging embedded applications require ever larger amount of data that have to be processed. Due to their large size, this data has to be stored off-chip in Dynamic Random Access Memories (DRAM). The challenges introduced by DRAMs in those systems are manifold. These include limited bandwidth and latency, as well as power consumption and reliability issues. In this talk, we will give an overview on various optimization techniques to optimize bandwidth, power and reliability in DRAM based and emerging memory systems.

Wednesday Plenary Speaker

Ram Kumar Krishnamurthy
Senior Research Director and Senior Principal Engineer
Intel Labs, USA

“Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities”

Ram Kumar Krishnamurthy received the B.E. degree in electrical engineering from the National Institute of Technology, Trichy, India, in 1993, the M.S. degree in electrical and computer engineering from the State University of New York, Buffalo, NY, USA, in 1994, and the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA, in 1997. He has been at Intel Corporation since 1997. He is currently a Senior Principal Engineer at Circuits Research Lab, Intel Labs, Hillsboro, OR, USA, where he heads the High-Performance and Low-Voltage Circuits Research Group. In this role, he leads research in high-performance, energy-efficient, and low-voltage circuits for next generation microprocessors, accelerators, and Systems-On-Chip (SoCs). He has led circuit technology research directions in high speed arithmetic units, on-chip interconnects, reconfigurable computing, energy efficient clocking, ultra low voltage design, hardware security, compute-in-memory, neuromorphic computing, and machine learning accelerators. He has made circuit technology contributions to multiple generations of Intel’s data center, client, FPGA, IoT, and AI products spanning across 180nm to 7nm process technology nodes. Krishnamurthy has filed 300 patents and holds 160 issued patents. He has published 200 papers and four book chapters on high-performance and energy-efficient circuits. He serves as the Chair of the Semiconductor Research Corporation (SRC) Technical Advisory Board for the circuit design thrust. He served as the Technical Program Chair and the General Chair of the IEEE International Systems-on-Chip Conference and presently serves on the Conference’s Steering Committee. He is an Adjunct Faculty with the Electrical and Computer Engineering Department, Oregon State University, Corvallis, OR, USA, where he taught advanced VLSI design. Krishnamurthy has received two Intel Achievement Awards for pioneering the first 64-bit Sparse-Tree ALU Technology and the first Advanced Encryption Standard hardware security accelerator on Intel products. He has received the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award, the IEEE European Solid State Circuits Conference Best Paper Award, the Outstanding Industry Mentor Award from SRC, Intel awards for most patents filed and most patents issued, the Intel Labs Gordon Moore Award, the Alumni Recognition Award from Carnegie Mellon University, the Distinguished Alumni Award from the State University of New York, MIT Technology Review’s TR35 Innovator Award, and was recognized as a top ISSCC paper contributor. He has served as a Distinguished Lecturer of the IEEE Solid-State Circuits Society, a Guest Editor of the IEEE Journal of Solid-State Circuits, an Associate Editor of the IEEE Transactions on VLSI Systems, and on the Technical Program Committees of ISSCC, CICC, and SOCC conferences. He is a Fellow of the IEEE and a Board Member of the Industry Advisory Board for the State University of New York.

Abstract: This talk will highlight some of the emerging challenges and opportunities for next generation nanoscale machine learning and hardware security technologies in the rapidly evolving loT industry. New and emerging loT markets for autonomous vehicles, drones and wearables require even higher performance and security at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient multi-core microprocessors and SoCs in the sub-10nm technology nodes will be outlined. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for nearest­ neighbor computing and reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic and memory circuits, on-chip interconnect fabric circuits, ultra-lightweight encryption engines, physically unclonable functions and fully-digital random number generator security building blocks are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed.

Thursday Keynote Speaker

Massimo Alioto
Professor, head of Green IC group, and Director of Integrated Circuits and Embedded Systems
National University of Singapore, Singapore

“Survival of The Fittest: Circuits and Architectures for Computation with Wide Power-Performance Adaptation Beyond Voltage Scaling”

Massimo Alioto is with the ECE Department of the National University of Singapore, where he leads the Green IC group and the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL - Lausanne.

He is (co)author of 270+ publications on journals and conference proceedings, and three books with Springer. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies.

He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE CASS (2010-2012), Distinguished Lecturer (2009-2010), and members of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2022, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.

Abstract:Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the performance target. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation, beyond conventional voltage scaling or adaptive parallelism. In this context, systems being able to adapt to a wider performance-power range (“the fittest”) allow true continuous operation and adjustment to the power-performance profile required by the application (“survival”).
In this talk, new techniques that drastically extend the performance-power scalability of digital circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path. Adaptation to a very wide range of energy/power availability is also discussed, presenting demonstrations of always-on systems (e.g., microcontrollers, power management units) with power down to sub-nW, and duty-cycled operation down to pW range. As an orthogonal design dimension, “just-enough” adaptation to the application-level quality requirement is shown to further extend the performance-power range by an order of magnitude or more. Under this energy-quality scaling framework, quality is treated as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications (e.g., machine learning), contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.

Thursday Plenary Speaker

Jerome Tjia
Senior Director, Head of Development Centre
Infineon Technologies Asia Pacific Pte Ltd

“Anchoring Security in the Connected World”

Mr. Jerome Tjia has 30 year experience in the semiconductor industry and was appointed as Head of Development Centre, Infineon Technologies Asia Pacific in January 2011. He is responsible for product development activities of Infineon’s Automotive, Power Management & Multi-market and Digital Security Solutions business divisions. He chairs the Infineon Asia Innovation Council that fosters innovation culture, technical ladder and project management careers in the Asia region.

Jerome Tjia is also active in the Singapore semiconductor industry ecosystem and University engagement. He is a board member of Singapore Semiconductor Industry Association since 2009. He also represents the semiconductor industry as a member of Advisory Committee of Republic Polytechnic and a member of Departmental Consultative Committee of the National University of Singapore.

Jerome holds a Master degree in Electrical Engineering from National University of Singapore and graduated with First Class Honors in Electrical Engineering from the University of New South Wales, Australia. He holds 12 US patents and speaks English, Chinese and Bahasa Indonesia.

Abstract:The keynote will talk about the explosive growth opportunity of IoT and the corresponding importance of security. Security is as good as the weakest link and therefore anchoring with a dedicated hardware security component is essential.

Banquet Speaker

to be announced