SOCC 2019 Tutorial Day Program

September 3, 2019

T1 (Room: Melati Main 4002)

Design of Ultra-low Power SRAMs for IoT, security and Computation-in-Memory
Tony Kim Tae Hyoung, Nanyang Technological University, Singapore

Abstract: Recently, various ultra-low power applications such as Internet-of-Things (IoT), wearable devices, biomedical devices, AI, and machine learning have emerged opening up a new domain of integrated circuits design. In these applications, ultra-low voltage circuit techniques for improving the power and energy efficiencies have been the main research focus. One of the most challenging functional blocks in ultra-low power systems is memory where SRAMs are dominantly employed. Since SRAMs occupy majority of the power in those systems, design of ultra-low power SRAMs is a critical task for power and energy efficiencies. In addition, SRAMs have started to be employed in realizing Physically Unclonable Function (PUF) and Computation-in-Memory (CIM). Even though basic SRAM design methodologies can be adopted in these applications, several additional design challenges need to be carefully addressed. This tutorial will present the basics in ultra-low power SRAMs followed by state-of-the-art ultra-low power SRAM design techniques. Design challenges and several methodologies for SRAM-based PUFs and SRAM-based CIM will also be explained. Finally, I will discuss future directions in ultra-low power SRAMs including various emerging non-volatile memory devices such as STTRAM, RRAM, etc.

Biography: Prof. Tony T. Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007 ~ 2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on isolated NBTI/PBTI measurement circuits and SRAM Mismatch measurement test structure, and battery backed memory design, respectively. In November 2009, he joined Nanyang Technological University as an assistant professor.
Prof. Kim received 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from U. of Minnesota, 2008 DAC/ISSCC Student Design Contest Award, 2008 Samsung Humantec Thesis Award (Bronze Prize), 2005 ETRI Journal Paper of the Year Award, 2001 Samsung Humantec Thesis Award (Honor Prize), and 1999 Samsung Humantec Thesis Award (Silver Prize). His current research interests include low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage sub-threshold circuit design for energy efficiency, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He is a member of IEEE.

T2  (Room: Melati Main 4002)

Internet of Things (IoT): Signals, Communications, Applications, Challenges, and Future Research
Ahmed Abelgawad, Central Michigan University, USA

Abstract: Internet of Things (IoT) is the network of physical objects or “things” embedded with electronics, software, sensors, and network connectivity. It enables the objects to collect, share, and analyze data. The IoT has become an integral part of our daily lives through applications such as public safety, intelligent tracking in transportation, industrial wireless automation, personal health monitoring, and health care for the aged community. IoT is one of the latest technologies that will change our lifestyle in the coming years. Experts estimate that as of now, there are 23 billion connected devices, and by 2020 it would reach 30 billion devices. This tutorial aims to introduce the design and implementation of IoT systems. The foundations of IoT will be discussed throughout real applications. Challenges and constraints for future research in IoT will be discussed. In addition, research opportunities and collaboration will be offered for the attendees.

Biography: Dr. Ahmed Abdelgawad received his M.S. and Ph.D. degree in Computer Engineering from University of Louisiana at Lafayette in 2007 and 2011 and subsequently joined IBM as a Design Aids & Automation Engineering Professional at Semiconductor Research and Development Center. In Fall 2012 he joined Central Michigan University as a Computer Engineering Assistant Professor. In Fall 2017, Dr. Abdelgawad was early promoted as a Computer Engineering Associate Professor. His area of expertise is distributed computing for Wireless Sensor Network (WSN), Internet of Things (IoT), Structural Health Monitoring (SHM), data fusion techniques for WSN, low power embedded system, video processing, digital signal processing, Robotics, RFID, Localization, VLSI, and FPGA design. He has published two books and more than 65 articles in related journals and conferences. Dr. Abdelgawad served as a reviewer for several conferences and journals, including IEEE WF-IoT, IEEE ISCAS, IEEE SAS, Springer, Elsevier, IEEE Transactions on VLSI, and IEEE Transactions on I&M. He severed in the technical committees of IEEE ISCAS 2007, IEEE ISCAS 2008, and IEEE ICIP 2009 conferences. He served in the administration committee of IEEE SiPS 2011. Dr. Abdelgawad has been appointed as a Track Chair of the International Conference on Cognitive and Sensor Networks (MIC-CSN 2013). He also served in the organizing committee of ICECS2013 and 2015 IEEE ICECS2015. Dr. Abdelgawad is the publicity chair in North America of the IEEE WF-IoT 2016/18 conferences. He is the finance chair of the IEEE ICASSP 2017. He is the TPC Co– Chair of IoT International Innovation Conference 2017 (I3C'17), the TPC Co– Chair of Global Internet of Things Summit (GIoTS 2017), and the technical program chair of IEEE MWSCAS 2018. He is currently the IEEE Northeast Michigan section chair and IEEE SPS Internet of Things (IoT) SIG Member. In addition, Dr. Abdelgawad served as a PI and Co-PI for several funded grants from NSF.

T3  (Room: Melati Main 4003)

AI Chip Technologies and DFT Methodologies
Yu Huang and Rahul Singhal, Mentor, A Siemens Business, USA

Abstract: Hardware acceleration for Artificial Intelligence (AI) is now a very competitive and rapidly evolving market. In this tutorial, we will start by covering the basics of deep learning. We will proceed to give an overview of the new and exciting field of using AI chips to accelerate deep learning computations. It will cover the critical and special characteristics and the architecture of the most popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips and speeding up time-to-market. Finally, we will present a few case studies on how DFT is implemented on the real AI chips.

Biography: Dr. Yu Huang is a Principal Engineer in the Silicon Test Systems Division of Mentor, A Siemens Business. His research interests include VLSI SoC testing, ATPG, compression and diagnosis. He holds 27 US patents and has 11 patents pending. He has published more than 110 papers in leading IEEE Journals, conferences and workshops. He is a senior member of the IEEE. He has served as technical program committee member for DAC, ITC, SOCC, ATS, ETS, ASPDAC, NATW and other conferences and workshops in the testing area. He received a Ph.D. from the University of Iowa in 2002.

Biography: Rahul Singhal is a Technical Marketing Engineer with Tessent Solutions group of Mentor, A Siemens Business. His focus is on the industry requirements in the areas of ATPG, compression, low pin count testing and DFT for AI chips architectures. He is currently a program committee member of NATW. Rahul received his M.S. in Electrical and Computer Engineering from Portland State University in 2011.

T4  (Room: Melati Main 4003)

Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test
Manoj Sachdev, University of Waterloo, Canada

Abstract: Static Random Access Memories (SRAMs) often occupy a significant area of contemporary Systems on Chip (SoC) integrated circuits (ICs) and therefore determine their energy consumption, yield, and reliability. The sense amplifier (SA) is a critical SRAM circuit that requires careful design. The offset in the SA does not scale well with technology scaling and has become an impediment to realizing energy efficient SRAMs. Additionally, the offset in SAs can also give rise to intermittent failures (soft-failures) in SRAMs that are difficult to detect through traditional march test algorithms.
This tutorial is divided into two parts. The first part focuses on SA design and contrasts techniques for mitigating SA offset voltage. The second part addresses SRAM design and test considerations for the SA offset voltage. Traditional approaches of SRAM testing are inadequate to cover SA offset related failures, and we highlight algorithmic and Design for Testability (DfT) techniques for detecting such failures. The tutorial draws data from several different publications, as well as from several test chips designed by the presenter and his graduate students.

Biography: Manoj Sachdev is a professor in electrical and computer engineering department at university of waterloo, Canada. His research interests include low power and high performance digital circuit design, mixed-signal circuit design, test and manufacturing issues of integrated circuits. He has written a book, two book chapters on testing and has published significantly in conferences and journals. He received the best paper award for his paper in European Design and Test Conference, 1997 and an honorable mention award for his paper in International Test Conference, 1998. He holds more than 10 granted and several pending US patents in the area of VLSI design and test. He is a senior member of IEEE.
He received his B.E. degree (with Honors) in electronics and communication engineering from University of Roorkee (India), and Ph.D. from Brunel University (UK). He was with Semiconductor Complex Limited, Chandigarh (India) from 1984 till 1989 where he designed CMOS Integrated Circuits. From 1989 till 1992, he worked in the ASIC division of SGS-Thomson at Agrate (Milan). In 1992, he joined Philips Research Laboratories, Eindhoven, where he researched on various aspects of VLSI testing and manufacturing.